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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Rev. 07 -- 13 November 2006 Product data sheet
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I2C-bus address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9554/PCA9554A open-drain interrupt output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554 except that the fixed I2C-bus address is different allowing up to sixteen of these devices (eight of each) on the same I2C-bus/SMBus.
2. Features
I I I I I I I I I I Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 8 I/O pins which default to 8 inputs 0 Hz to 400 kHz clock frequency
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16, HVQFN16 (2 versions: 4 x 4 x 0.85 mm and 3 x 3 x 0.85 mm), and bare die
3. Ordering information
Table 1. Ordering information Tamb = -40 C to +85 C. Type number PCA9554N PCA9554AN PCA9554D PCA9554AD PCA9554DB PCA9554ADB PCA9554TS PCA9554ATS PCA9554PW PCA9554APW PCA9554BS PCA9554ABS PCA9554BS3 PCA9554ABS3 PCA9554U Topside mark PCA9554N PCA9554AN PCA9554D PCA9554AD 9554DB 9554A PCA9554 PA9554A 9554DH 9554ADH 9554 554A P54 54A bare die HVQFN16 HVQFN16 TSSOP16 SSOP20 SSOP16 SO16 Package Name DIP16 Description plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 7.5 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm Version SOT38-1 SOT162-1 SOT338-1 SOT266-1 SOT403-1 SOT629-1 SOT758-1 -
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
2 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
4. Block diagram
PCA9554/PCA9554A
A0 A1 A2 8-bit SCL SDA INPUT FILTER I2C-BUS/SMBus CONTROL write pulse VDD POWER-ON RESET read pulse INPUT/ OUTPUT PORTS IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 VDD
VSS LP FILTER
002aac492
INT
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554/PCA9554A
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
3 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
5. Pinning information
5.1 Pinning
PCA9554N PCA9554AN
A0 A1 A2 IO0 IO1 IO2 IO3 VSS 1 2 3 4 5 6 7 8
002aac485
16 VDD 15 SDA 14 SCL A0 13 INT 12 IO7 11 IO6 10 IO5 9 IO4 A1 A2 IO0 IO1 IO2 IO3 VSS 1 2 3 4 5 6 7 8
002aac486
16 VDD 15 SDA 14 SCL 13 INT 12 IO7 11 IO6 10 IO5 9 IO4
PCA9554D PCA9554AD
Fig 2. Pin configuration for DIP16
Fig 3. Pin configuration for SO16
A0 A1 A2 IO0 IO1 IO2 IO3 VSS
1 2 3 4 5 6 7 8
002aac487
16 VDD 15 SDA 14 SCL 13 INT 12 IO7 11 IO6 10 IO5 9 IO4
A0 A1 A2 IO0 IO1 IO2 IO3 VSS
1 2 3 4 5 6 7 8
002aac488
16 VDD 15 SDA 14 SCL 13 INT 12 IO7 11 IO6 10 IO5 9 IO4
PCA9554DB PCA9554ADB
PCA9554PW PCA9554APW
Fig 4. Pin configuration for SSOP16
Fig 5. Pin configuration for TSSOP16
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
4 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
INT SCL n.c. SDA VDD A0 A1 n.c. A2
1 2 3 4 5 6 7 8 9
20 IO7 19 IO6 18 n.c. 17 IO5 16 IO4 15 VSS 14 IO3 13 n.c. 12 IO2 11 IO1
002aac489
PCA9554TS PCA9554ATS
IO0 10
Fig 6. Pin configuration for SSOP20
PCA9554BS PCA9554ABS
13 SDA 14 VDD 16 A1 15 A0 terminal 1 index area terminal 1 index area
PCA9554BS3 PCA9554ABS3
13 SDA 12 SCL 11 INT 10 IO7 9 5 6 7 8 IO6 IO5 14 VDD IO4 16 A1 1 2 3 4 IO3 15 A0 VSS
A2 IO0 IO1 IO2
1 2 3 4 5 6 7 8
12 SCL 11 INT 10 IO7 9 IO6
A2 IO0 IO1 IO2
VSS
IO3
IO4
IO5
002aac490
002aac491
Transparent top view
Transparent top view
Fig 7. Pin configuration for HVQFN16 (SOT629-1)
Fig 8. Pin configuration for HVQFN16 (SOT758-1)
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
5 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
5.2 Pin description
Table 2. Symbol Pin description Pin DIP16, SO16, SSOP16, TSSOP16 A0 A1 A2 IO0 IO1 IO2 IO3 VSS IO4 IO5 IO6 IO7 INT SCL SDA VDD n.c.
[1]
Description HVQFN16 SSOP20 15 16 1 2 3 4 5 6[1] 7 8 9 10 11 12 13 14 6 7 9 10 11 12 14 15 16 17 19 20 1 2 4 5 3, 8, 13, 18 address input 0 address input 1 address input 2 input/output 0 input/output 1 input/output 2 input/output 3 supply ground input/output 4 input/output 5 input/output 6 input/output 7 interrupt output (open-drain) serial clock line serial data line supply voltage not connected
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -
HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
6. Functional description
Refer to Figure 1 "Block diagram of PCA9554/PCA9554A".
6.1 Registers
6.1.1 Command byte
Table 3. Command 0 1 2 3 Command byte Protocol read byte read/write byte read/write byte read/write byte Function Input Port register Output Port register Polarity Inversion register Configuration register
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
6 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default `X' is determined by the externally applied logic level, normally `1' when no external signal externally applied because of the internal pull-up resistors.
Table 4. Bit 7 6 5 4 3 2 1 0 I7 I6 I5 I4 I3 I2 I1 I0 Register 0 - Input Port register bit description Symbol Access read only read only read only read only read only read only read only read only Value X X X X X X X X Description determined by externally applied logic level
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Register 1 - Output Port register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Access R R R R R R R R Value 1* 1* 1* 1* 1* 1* 1* 1* Description reflects outgoing logic levels of pins defined as outputs by Register 3
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
7 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with `1'), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a `0'), the Input Port data polarity is retained.
Table 6. Register 2 - Polarity Inversion register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* Description inverts polarity of Input Port register data 0 = Input Port register data retained (default value) 1 = Input Port register data inverted
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD.
Table 7. Register 3 - Configuration register bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description configures the directions of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value)
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9554/PCA9554A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9554/PCA9554A registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage.
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
8 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS.
data from shift register configuration register data from shift register write configuration pulse D FF CK Q D FF Q Q Q1
100 k
output port register data VDD
IO0 to IO7 write pulse CK output port register input port register D FF read pulse CK polarity inversion register data from shift register write polarity pulse D FF CK
002aac493
Q2 VSS
Q
input port register data to INT
Q
polarity inversion register data
Remark: At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of IO0 to IO7
PCA9554_9554A_7
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Product data sheet
Rev. 07 -- 13 November 2006
9 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.5 Device address
slave address 0 1 0 0 A2 A1 A0 R/W 0 1 slave address 1 1 A2 A1 A0 R/W
fixed
hardware selectable
002aac494
fixed
programmable
002aac495
Fig 10. PCA9554 device address
Fig 11. PCA9554A device address
6.6 Bus transactions
Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 12 and Figure 13. Data is read from the PCA9554/PCA9554A registers using the Read mode as shown in Figure 14 and Figure 15. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
SCL
1
2
3
4
5
6
7
8
9 command byte A 0 0 0 0 0 0 0 1 A data to port DATA 1 A acknowledge from slave P STOP condition
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W acknowledge from slave write to port
START condition
acknowledge from slave
tv(Q) data out from port data 1 valid
002aac472
Fig 12. Write to Output Port register
SCL
1
2
3
4
5
6
7
8
9 command byte A 0 0 0 0 0 0 1 1/0 A data to register DATA A acknowledge from slave P STOP condition
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W acknowledge from slave
START condition
acknowledge from slave
data to register
002aac473
Fig 13. Write to Configuration register or Polarity Inversion register
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
10 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W acknowledge from slave slave address (cont.) S 0 1 0 0 A2 A1 A0 1 R/W acknowledge from slave A A command byte A (cont.)
START condition
acknowledge from slave data from register DATA (first byte) A data from register DATA (last byte) NA P STOP condition
(repeated) START condition
acknowledge from master
no acknowledge from master
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter
002aac474
Fig 14. Read from register
SCL
1
2
3
4
5
6
7
8
9 data from port A DATA 1 A acknowledge from master data from port DATA 4 NA P STOP condition
slave address SDA S 0 1 0 0 A2 A1 A0 1 R/W acknowledge from slave
START condition
no acknowledge from master
read from port data into port tv(INT_N) INT
th(D) DATA 2 trst(INT_N) DATA 3
tsu(D) DATA 4
002aac475
This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition.
Fig 15. Read Input Port register
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
11 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
7. Application design-in information
VDD (5 V)
10 k 10 k 10 k 10 k 2 k
VDD MASTER CONTROLLER SCL SDA
VDD
PCA9554
SCL SDA IO0 IO1 IO2 IO3 IO4
SUBSYSTEM 1 (e.g., temp. sensor) INT RESET SUBSYSTEM 2 (e.g., counter) A enable controlled switch (e.g., CBT device) B
INT VSS
INT
IO5 IO6 IO7 A2 A1 A0 VSS
ALARM SUBSYSTEM 3 (e.g., alarm system)
VDD
002aac496
Device address configured as 0100 100X for this example. IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6 and IO7 are not used and must be configured as outputs.
Fig 16. Typical application
8. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD II VI/O IO(IOn) IDD ISS Ptot Tstg Tamb Parameter supply voltage input current voltage on an input/output pin output current on pin IOn supply current ground supply current total power dissipation storage temperature ambient temperature operating Conditions Min -0.5 VSS - 0.5 -65 -40 Max +6.0 20 5.5 50 85 100 200 +150 +85 Unit V mA V mA mA mA mW C C
PCA9554_9554A_7
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Product data sheet
Rev. 07 -- 13 November 2006
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
9. Static characteristics
Table 9. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD Istb supply voltage supply current standby current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V; VDD = 2.3 V VOL = 0.7 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.7 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V VOL = 0.7 V; VDD = 4.5 V VOH HIGH-level output voltage IOH = -8 mA; VDD = 2.3 V IOH = -10 mA; VDD = 2.3 V IOH = -8 mA; VDD = 3.0 V IOH = -10 mA; VDD = 3.0 V IOH = -8 mA; VDD = 4.75 V IOH = -10 mA; VDD = 4.75 V IIH IIL Ci Co IOL input leakage current input leakage current input capacitance output capacitance LOW-level output current VOL = 0.4 V VDD = 3.6 V; VI = VDD VDD = 5.5 V; VI = VSS
[2] [2] [2] [2] [2] [2] [3] [3] [3] [3] [3] [3]
Parameter
Conditions
Min 2.3 [1]
Typ 104 550 0.25 1.5 6 6 10 13 14 19 17 24 3.7 3.7 -
Max 5.5 175 700 1 1.65 +0.3VDD 5.5 +1 10 +0.8 5.5 1 -100 5 5 -
Unit V A A A V V V mA A pF V V mA mA mA mA mA mA V V V V V V A A pF pF mA
power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance
no load; VI = VDD or VSS
-0.5 0.7VDD
Input SCL; input/output SDA
VOL = 0.4 V VI = VDD = VSS VI = VSS
3 -1 -0.5 2.0 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 3
Interrupt INT
PCA9554_9554A_7
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
13 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Table 9. Static characteristics ...continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIL VIH ILI
[1] [2] [3]
Parameter LOW-level input voltage HIGH-level input voltage input leakage current
Conditions
Min -0.5 2.0 -1
Typ -
Max 0.8 5.5 1
Unit V V A
Select inputs A0, A1, A2
VDD must be lowered to 0.2 V in order to reset part. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics
Table 10. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD:ACK tVD;DAT tSU;DAT tLOW tHIGH tr tf tSP Port timing tv(Q) tsu(D) th(D) tv(INT_N) trst(INT_N)
[1] [2] [3]
Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 0.9 300 300 50
Unit
Max 100 3.45 1000 300 50
SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter data output valid time data input setup time data input hold time valid time on pin INT reset time on pin INT
[1] [2]
0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -
kHz s s s s s s ns ns s s ns s ns
100 1 -
200 4 4
100 1 -
200 4 4
ns ns s s s
Interrupt timing
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. Cb = total capacitance of one bus line in pF.
(c) NXP B.V. 2006. All rights reserved.
PCA9554_9554A_7
Product data sheet
Rev. 07 -- 13 November 2006
14 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 17. Definition of timing
PCA9554_9554A_7
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Product data sheet
Rev. 07 -- 13 November 2006
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
11. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.02 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001 JEITA SC-503-16 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 18. Package outline SOT38-1 (DIP16)
PCA9554_9554A_7 (c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 -- 13 November 2006
16 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITA EUROPEAN PROJECTION A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8o o 0
ISSUE DATE 99-12-27 03-02-19
Fig 19. Package outline SOT162-1 (SO16)
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Product data sheet
Rev. 07 -- 13 November 2006
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 20. Package outline SOT338-1 (SSOP16)
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Product data sheet
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 o 0
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC MO-152 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 21. Package outline SOT266-1 (SSOP20)
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Product data sheet
Rev. 07 -- 13 November 2006
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 22. Package outline SOT403-1 (TSSOP16)
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
D
B
A
terminal 1 index area E
AA 1 c
detail X
e1
1/2 e
C b 8 vMCAB wMC y1 C y
e 5 L
4
9 e
Eh
1/2 e
e2
1 12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.38 0.23 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.65 e1 1.95 e2 1.95 L 0.75 0.50 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT629-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 23. Package outline SOT629-1 (HVQFN16)
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Product data sheet
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
D
B
A
terminal 1 index area
E
A A1 c
detail X
e1
1/2 e
C vMCAB wM C 8 y1 C y
e 5 L 4
b
9 e
Eh
1/2 e
e2
1
12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.75 1.45 E (1) 3.1 2.9 Eh 1.75 1.45 e 0.5 e1 1.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT758-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21
Fig 24. Package outline SOT758-1 (HVQFN16)
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Product data sheet
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
12. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
13. Soldering
13.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
13.2 Through-hole mount packages
13.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
13.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
13.3 Surface mount packages
13.3.1 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 12. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25.
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
13.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
13.4 Package related soldering information
Table 13. Mounting Through-hole mount Through-hole-surface mount Suitability of IC packages for wave, reflow and dipping soldering methods Package[1] CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[4] Soldering method Wave suitable suitable[3] not suitable Reflow[2] - - not suitable Dipping - suitable -
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Table 13. Mounting
Suitability of IC packages for wave, reflow and dipping soldering methods ...continued Package[1] HTSSON..T[5], Soldering method Wave Reflow[2] suitable Dipping -
Surface mount
not suitable BGA, LBGA, LFBGA, SQFP, SSOP..T[5], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[10], WQCCN..L[10] not suitable[6]
suitable
-
suitable not not recommended[7][8] recommended[9]
suitable suitable suitable not suitable
- - - -
not suitable
[1] [2]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[3] [4] [5]
[6]
[7] [8] [9]
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
14. Abbreviations
Table 14. Acronym ACPI CDM CMOS ESD FET GPIO HBM I2C-bus I/O LED MM PCB POR SMBus Abbreviations Description Advanced Configuration and Power Interface Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge Field-Effect Transistor General Purpose Input/Output Human Body Model Inter-Integrated Circuit bus Input/Output Light-Emitting Diode Machine Model Printed-Circuit Board Power-On Reset System Management Bus
PCA9554_9554A_7
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Product data sheet
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
15. Revision history
Table 15. Revision history Release date 20061113 Data sheet status Product data sheet Change notice Supersedes PCA9554_9554A_6 Document ID PCA9554_9554A_7 Modifications:
* * * * * * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added HVQFN16 (SOT758-1) and bare die package offerings Pin names I/O0 through I/O7 changed to IO0 through IO7 Table 2 "Pin description": added Table note 1 and its reference at HVQFN pin 6 (VSS) Symbol (tpv and tPV) changed to tv(Q) Symbol (tph and tPH) changed to th(D) Symbol (tps and tPS) changed to tsu(D) Symbol (tiv and tIV) changed to tv(INT_N) Symbol (tir and tIR) changed to trst(INT_N) Figure 16 "Typical application" modified (deleted "PCA9554A") Table 8 "Limiting values": - Changed parameter description for symbol VI/O from "DC voltage on an I/O" to "voltage on an input/output pin" - Changed symbol "II/O, DC output current on an I/O" to "IO(IOn), output current on pin IOn" - Changed parameter description of ISS from "supply current" to "ground supply current"
* *
PCA9554_9554A_6 (9397 750 13289) PCA9554_9554A_5 (9397 750 10163) PCA9554_9554A_4 (9397 750 09817) PCA9554_9554A_3 (9397 750 08342) PCA9554_9554A_2 (9397 750 08209) PCA9554_9554A_1 (9397 750 08159)
Table 9 "Static characteristics": - Symbols "Istbl" and "Istbh" replaced with "Istb" Added Section 14 "Abbreviations" Product data Product data Product specification Product specification Product specification Product specification PCA9554_9554A_5
20040930 20020726 20020513 20010507 20010319 20010319
853-2243 28672 of PCA9554_9554A_4 26 July 2002 PCA9554_9554A_3 PCA9554_9554A_2 PCA9554_9554A_1 -
PCA9554_9554A_7
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Product data sheet
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
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PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 6.5 6.6 7 8 9 10 11 12 13 13.1 13.2 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.3.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register 0 - Input Port register . . . . . . . . . . . . . 7 Register 1 - Output Port register. . . . . . . . . . . . 7 Register 2 - Polarity Inversion register . . . . . . . 8 Register 3 - Configuration register . . . . . . . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device address . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Handling information. . . . . . . . . . . . . . . . . . . . 23 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Through-hole mount packages . . . . . . . . . . . . 23 Soldering by dipping or by solder wave . . . . . 23 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23 Surface mount packages . . . . . . . . . . . . . . . . 23 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25 Package related soldering information . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contact information. . . . . . . . . . . . . . . . . . . . . 29 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2006 Document identifier: PCA9554_9554A_7

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